Driving 7-segment LEDs from an FPGA.
The Cyclone II development board from Altera has two 7-segment LED displays which can be very useful for monitoring control variables.
Driving the displays is straight-forward, the four bit binary data can be translated using a 'case' statement to provide the look-up table function. For example,
case Hex1[3..0] is
when 0 =>
7seg1[7..0] = H"C0";
when 1 =>
7seg1[7..0] = H"F9";
when 2 =>
7seg1[7..0] = H"A4";
when 3 =>
7seg1[7..0] = H"B0";
when 4 =>
7seg1[7..0] = H"99";
when 5 =>
7seg1[7..0] = H"92";
when 6 =>
7seg1[7..0] = H"82";
when 7 =>
7seg1[7..0] = H"F8";
when 8 =>
7seg1[7..0] = H"80";
when 9 =>
7seg1[7..0] = H"98";
when 10 =>
7seg1[7..0] = H"88";
when 11 =>
7seg1[7..0] = H"83";
when 12 =>
7seg1[7..0] = H"C6";
when 13 =>
7seg1[7..0] = H"A1";
when 14 =>
7seg1[7..0] = H"86";
when 15 =>
7seg1[7..0] = H"8E";
end case;
7seg1[7..0] is declared as a NODE in the design.
7seg1[7..0] : NODE;
7seg1[7..0] : OUTPUT; -- 7 segment display (0=LED on)
Hex1[3..0] is the binary data you wish to display. All that remains is to map the 7seg1[7..0] to the appropriate outputs of the FPGA, (this is for the Cyclone II board).
7seg1[7] Output PIN_AC11
7seg1[6] Output PIN_AD10
7seg1[5] Output PIN_AF10
7seg1[4] Output PIN_AE10
7seg1[3] Output PIN_AE11
7seg1[2] Output PIN_AD11
7seg1[1] Output PIN_V13
7seg1[0] Output PIN_V14
It is just necessary to repeat the above to use the second display.
7seg0[7] Output PIN_U12
7seg0[6] Output PIN_V11
7seg0[5] Output PIN_Y12
7seg0[4] Output PIN_AA12
7seg0[3] Output PIN_AE12
7seg0[2] Output PIN_AD12
7seg0[1] Output PIN_AF13
7seg0[0] Output PIN_AE13