DP1 accepts analogue video, either standard or high definition, which it filters and buffers using a Analog Devices ADA4411 IC, before clamping and converting to digital video using Analog Devices AD9981 triple ADC device. The input video can be composite (although decoding must be done in the FPGA), B/W video, or YPbPr or RGB format. The ADCs can operate up to 80MHz sample rate and provide 10-bit output data for the FPGA. In addition the synchronizing signals are stripped off the incoming composite sync and are filtered to provide horizontal and vertical timing information to the FPGA. A programmable line locked clock is also provided. Control of this IC is via the I2C bus.

On the video output side, digital video is output from the FPGA to an Analog Devices ADV7321 video digital to analog converter/video encoder IC. The digital video can be converted to analogue YPbPr or RGB signals using 12 bit DACs at standard or high definition. In addition the IC can also encode the video to either PAL or NTSC composite standards. The outputs are filtered and buffered using an Analog Devices ADA4412 IC.Again the IC is controlled via the I2C bus, and a number of filters are available internally.

An Analog Devices ADAU1326 audio codec is used for the audio channels. Stereo analog audio is converted using 24bit ADCs at either 44.1, 48, or 96kHz. The output I2S formatted data is sent to the FPGA. I2S data from the FPGA is then sent to the audio DAC where is is converted back to analogue using 24 bit DACs. Again this IC is controlled using I2C bus.

The board plugs into the two Santa Cruz connectors that are provided on both of the Cyclone development boards and derives all the power supplies it requires on board from the raw supplies provided by those boards.

DP1 Schematics

DP1 PCB Layout

DP1 Instruction manual

AD9981 datasheet

ADV7321 datasheet

ADAU1326 datasheet

DP1 Pin Assignments

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DP1 Register maps