PT8: Multi-standard video encoder IP core

PT13: Very compact microprocessor IP core

PT6: Video Pattern Generator IP core

This IP block provides a simple write only controller for the I2C bus, using just 77 logic elements and some memory or latches for the I2C register data. The design requires only a clock and reset and provides SDA and SCL output lines.

To download the controller, click on the zip file icon in the panel on the right and save to disc. Unzip the files in your chosen directory and you are ready to go. The download provides the symbol file, the AHDL (Altera high level description language) file I2C_controller.tdf and an example memory file, I2C_ROM.mif. Verilog versions of the two files can also be downloaded from the panel on the right. To write to an I2C device it is first necessary to send a start condition (a unique condition for the SDA and SCL lines), followed by the unique device address (a 7-bit word), followed by the read/write bit (=0 to write to a device). The device then acknowledges if the address is valid. Next the master then sends a register address (the registers are usually indirectly addressed using an internal address register), and finally the data, starting with the data for the first register, (again most I2C devices auto-increment the register address after each register has been written). Finally when all the registers have been written a stop condition is sent (again a unique state for the SDA and SCL lines) and the bus is freed. The I2C controller consists of two counters, I2C_Byte_count and I2C_sequencer. The former counter addresses the memory where the I2C register values are kept. On reset this counter is set to 0 and addresses location $00 in the memory. The counter value is decoded and if zero this signals a start condition to be performed on the I2C bus. The I2C_sequencer counter then starts and in turn, its values are decoded, each value setting or resetting the SCL and SDA bit according to the requirement. When the I2C sequencer gets to value 9 it stops and the I2C_Byte_count is incremented. The next value read from the memory is the I2C address of the device. Again the I2C_sequencer counter serializes the memory value as well as receiving the acknowledge clock from the device. Note that this simple I2C controller does not check if the acknowledge is valid and sends the information ‘blind’. The next byte is usually the register address value for the I2C device, and the following bytes are the corresponding values for the rest of the registers. When all of the registers of the device have been written to, the decoded I2C_Byte_count counter signals a stop condition to be sent. If there are more devices in the system then the next value can signal another cycle to be initiated and so on until all the devices have had their registers loaded. When the last stop condition is sent the I2C_Byte_count is reset.In the download file we show the I2C values for one condition of the DP1 interface board. There are three I2C devices that require initialization and the data to be downloaded is contained in a file called I2C.ROM.mif (when compiling this software, please ensure that the lpm_ROM definition for this file is pointing at a valid location on your drive). A copy of the file is shown below.

Download I2C controller for Altera FPGAs

I2C bus specification

Verilog I2C files

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