PT29 is a PDC extractor IP core.
PT29 is a IP core designed to extract the Program Delivery Control, (PDC), information from line 16 of a PAL video signal. The intellectual property core accepts 8 bit BT656 formatted data from a video decoder, and the associated 27MHz clock, from which it slices and decodes the PDC information and stores it into registers.
Control and status registers are written to and read from using a conventional 8 bit wide microprocessor interface.
The PDC data format is described in the document ETSI EN 300 231 v.1.3.1 (2003-04): Television Systems; Specification of the domestic video Programme Delivery Control system (PDC), and in particular paragraphs 8.2.2.
The PDC data is transmitted on line 16 of PAL video standards and consists of bi-phase modulated data at a data rate of 2.5MHz.
he PT29 IP core assumes the PDC is formatted to a BT656 video stream with embedded TRS codes and with an associated 27MHz clock; typically this data would be from a video decoder and constitutes luma only content which is a digital representation of the composite un-processed video.
Please contact SingMai if you wish to arrange a demonstration of the core, enquiries@singmai.com.
The core is supplied as a compiled and encrypted design file for Altera FPGAs and the prices are for a one-off payment which allows unlimited use of the core for a period of 3 years. The core is supplied with 6 months telephone/e-mail support and a 3 year update and bug fix guarantee. After this time the IP core license can be renewed.
For other FPGA vendors, for ASIC applications and for alternative license arrangements please contact SingMai at the e-mail address above.
Logic Elements |
Memory Bits |
M4K blocks |
9x9 Multipliers |
18x18 multipliers |
289 |
0 |
0 |
0 |
0 |
Full information can be found in the user manual.
If you require any further information or a formal quotation please contact enquiries@singmai.com
Download the PT29 user manual
